Senior Member of Technical Staff
SWIR Vision Systems
IT
Bengaluru, Karnataka, India · Brno, Czechia · South Moravian Region, Czechia
Posted on Feb 11, 2026
Role Summary
We are seeking a Senior NVM Design Engineer with 15+ years of industry experience in OTP and/or EEPROM memory design to lead the architecture, design, and delivery of high-quality non-volatile memory IPs. This role requires deep technical expertise, strong cross-functional leadership, and ownership of NVM IPs from concept through silicon qualification and production release.
Key Responsibilities
Architecture & Design
- Lead architecture definition and circuit design of OTP and EEPROM memory IPs, including bit-cell, periphery, high-voltage devices, charge pumps, sense amplifiers, and write/erase control.
- Define programming algorithms, redundancy schemes, reliability mechanisms, and safety features.
- Drive PPA (Power, Performance, Area) optimization across multiple technology nodes.
- Own top-level NVM IP micro-architecture, including interfaces to digital controllers and test logic.
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
| We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work. |
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering or related field.
- 15+ years of hands-on experience in OTP and/or EEPROM memory design.
- Strong expertise in:
- NVM bit-cell and peripheral circuit design
- High-voltage devices and reliability-aware design
- Programming/erase algorithms and margin analysis
- Silicon debug and characterization
- Proficiency with SPICE simulation, corner analysis, and statistical modeling.
- Experience working across multiple process nodes and foundry technologies.
Preferred Qualifications
- Experience with both OTP and EEPROM (cell-based or fuse-based implementations).
- Familiarity with automotive or safety-critical requirements (AEC-Q100, ISO-26262).
- Exposure to NVM controllers, digital interfaces, and test vehicles.
- Prior experience leading IP tape-outs and production releases.
- Strong documentation and technical review skills.
Implementation & Silicon Execution
- Oversee schematic design, simulation, and verification (functional, corner, Monte-Carlo, aging).
- Partner closely with layout teams to ensure DRC/LVS clean, robust HV-aware layouts with strong EM/IR and reliability margins.
- Support DFT, BIST, IJTAG, and test-mode implementation, including fuse evaluation and trimming flows.
- Drive silicon bring-up, debug, and characterization, including programming window optimization and yield learning.
- Define and support qualification strategies (HTOL, bake, cycling, retention, endurance).
- Work with Quality & Reliability teams to ensure product readiness and cost-effective qualification.
- Own failure analysis and root-cause resolution for NVM-related issues.
Cross-Functional Leadership
- Act as technical lead interfacing with Technology Development, Digital Design, Validation, Product, and Foundry partners.
- Mentor junior and mid-level designers; establish best practices and design methodology for NVM IP.
- Contribute to multi-generation NVM roadmaps and technology scaling strategies.