Analog Design Manager (Power & Clock IP)
SWIR Vision Systems
Design
Allen, TX, USA
Posted on Feb 13, 2026
onsemi (Nasdaq: ON) is a global leader in intelligent power and sensing technologies, driving innovation to build a safer, cleaner, and smarter world. With a strong focus on automotive, industrial, and AI data center markets, we are shaping the future of vehicle electrification, sustainable energy, and advanced automation.
About the Treo Platform
The newly launched Treo Platform is a cutting-edge analog and mixed-signal solution built on 65nm Bipolar-CMOS-DMOS (BCD) technology. Supporting voltage ranges from 1–90V and operating temperatures up to 175°C, Treo is engineered for high-performance applications in automotive, medical, industrial, and AI data centers. Its modular architecture simplifies design, reduces system costs, and accelerates time-to-market. All products are manufactured at our state-of-the-art 300mm fab in East Fishkill, NY.
About the Role
We’re seeking an experienced Analog Design Team Manager to lead the development of power and clock analog IP blocks for platform-based SoC products on the Treo platform at onsemi. This role combines technical depth with strong people leadership: you’ll set IP strategy, define best-in-class design flows, drive IP delivery to product integration teams to enable execution to tape-out, and nurture a high-performing team. If you’re excited about how AI will transform analog design, you’ll have an opportunity to explore and pilot data-driven methods and tooling to elevate our design quality and velocity.
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.
onsemi is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, ethnicity, color, religion, ancestry, national origin, age, marital status, pregnancy, sex, sexual orientation, physical or mental disability, medical condition, genetic information, military or veteran status, gender identity, gender expression, or any other protected category under applicable federal, state, or local laws.
If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Talent.acquisition@onsemi.com for assistance.
Minimum Qualifications
- 10+ years of experience in analog IC design, with 5+ years in a management/leadership role.
- Proven track record architecting and designing power management and clocking analog IP for platform-based SoCs.
- Proficiency with modern analog simulators, tools, and flows (e.g., SPICE/AMS, Monte Carlo, corners/variability, noise/jitter analysis, reliability/EM/IR, RC extraction, mixed-signal co-sim).
- Solid understanding of device physics, analog architectures, layout-dependent effects, and process/PDK interactions across corners and aging.
- Experience leading cross-functional execution from concept to tape-out and post-silicon correlation.
- Strong communication skills; ability to influence stakeholders and represent the team in program reviews.
Preferred Qualifications
- Familiarity with mixed-signal verification, behavioral modeling (Verilog-A/AMS), and interface with digital verification environments.
- Hands-on exposure to AI/ML-assisted design or EDA automation; curiosity and structured thinking about integrating AI into analog methodologies.
- Experience building processes and metrics for team performance, design quality, and schedule predictability.
Success Metrics (What Good Looks Like)
- On-time delivery of first-pass silicon for power/clock subsystem IP with robust PVT coverage.
- Measurable improvements in power efficiency, phase noise/jitter, line/load regulation, and area across platform generations.
- Adoption of enhanced flows/tooling (including AI-assisted steps) that reduce cycle time or improve parametric yield.
- High employee engagement and retention; clear growth plans and skill development across the team.
Key Responsibilities
- Team Leadership & Talent Development
- Lead, mentor, and grow a team of 10–20 analog designers and layout engineers; set goals, conduct performance reviews, and build succession plans.
- Foster a culture of accountability, excellence, and collaboration, emphasizing design quality, schedule integrity, and cross-functional communication.
- Technical Ownership (Power & Clock IP)
- Own architecture, design, verification, and delivery of power management (LDOs, DC/DC, charge pumps) and clocking (PLLs, DLLs, oscillators, clock distribution) blocks for Treo-based SoC platforms.
- Define IP specifications, corner cases, and sign-off criteria; drive first-time-right silicon through rigorous pre-silicon analysis and post-silicon correlation.
- Deliver analog blocks into a digital on top subsystem ready for product integration
- Execution & Program Management
- Plan and manage project schedules, resources, and risk mitigation across multiple concurrent IPs; ensure milestones (spec, RTL/AMS integration, layout, tape-out) are met.
- Collaborate closely with digital design, verification, PDK/technology, validation/test, Functional Safety and product/operations teams to enable smooth platform integration.
- Tools, Flows & Quality
- Champion state-of-the-art analog simulators, tools, and flows (e.g., schematic capture, SPICE/AMS simulators, Monte Carlo/statistical analysis, electromigration/IR checks, reliability).
- Establish and maintain design methodologies, checklists, and data-driven dashboards for systematic reviews and sign-off.
- Innovation & AI
- Explore how AI/ML can augment analog workflows (e.g., design space exploration, model-order reduction, layout-aware optimization, testbench generation, corner selection, bug triage).
- Pilot and evaluate emerging solutions in partnership with EDA vendors and internal CAD/Methodology teams; define measurable outcomes for adoption.
- Post-Silicon & Customer Impact
- Support lab bring-up and silicon characterization; partner with validation to root-cause issues and drive corrective actions.
- Contribute to platform reuse strategy and documentation to accelerate future programs and improve customer experience.