Snr Physical Design Engineer
SWIR Vision Systems
Design
Bengaluru, Karnataka, India
Posted on Feb 27, 2026
Physical Design Engineer
As a Physical Implementation Engineer, you will play a leading ownership role in the physical design domain for developing ON Semiconductor’s cutting edge image sensor products. You will work on all aspects of the RTL-to-GDS flow including chip sign-off activities. You need to work closely with cross-functional teams like Digital logic design, Analog Design, IP Design, Packaging and Product/Test Engineering in determining architecture/specification, design integration and post-silicon validation support of the products.
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onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
| We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work. |
Responsibilities:
Responsibilities include participating in the efforts in establishing CAD and physical design methodologies, chip floor plan, power/clock distribution, chip assembly, synthesis and P&R, timing closure, power, noise analysis and back-end verification across multiple projects.
In this role you will be responsible for all aspects of chip signoff activities e.g. timing, physical & electrical verification. Also, resolve design and flow issues related to physical design, identify potential solutions and drive execution.
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Experience/Requirements:
- BSEE required, MSEE preferred with minimum 2-3 years of related work experience in physical design.
- Good understanding of ASIC physical design flow from synthesis to tape-out including hands-on experience in synthesis, floor planning, P&R, LVS/DRC, die area estimation, integration of hard IPs, ECO implementation, constraints management etc.
- Experience leading the block/chip-level implementation.
- Experience in the low-power design methodology is a big plus.
- Hands-on experience on EDA tools: Design Compiler, ICCII/Fusion Compiler, Conformal-LEC/Formality, Calibre LVS and DRC, Primetime-SI, Redhawk/Voltus.
- Good understanding of the library views used in the implementation process (lef, lib, def)
- Self-motivated and an ability to take ownership of the physical design activities.
- Excellent communication and interpersonal skills.
- Strong programming skills in TCL/Perl, methodology development and rollout processes are a plus.
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