Principal Engineer, Digital Design (IO Subsystem)
Design
Allen, TX, USA
Posted on Jun 19, 2026
Job Summary:
Job Description
We are seeking a Principal Digital Design Engineer based in Allen, TX, to own the IO subsystem for onsemi’s microcontroller platform. In this role, you will be responsible for defining, architecting, and delivering a highly configurable IO subsystem that supports a wide range of product requirements across multiple end markets.
This position plays a critical role in enabling platform scalability and product differentiation. The IO subsystem must be flexible, reusable, and optimized for performance, power, and area while supporting a wide range of product requirements.
The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system architecture, product lines, DFT, physical design, verification, and software teams. This role requires strong technical execution, cross-functional leadership, and the ability to influence platform direction.
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.
onsemi is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, ethnicity, color, religion, ancestry, national origin, age, marital status, pregnancy, sex, sexual orientation, physical or mental disability, medical condition, genetic information, military or veteran status, gender identity, gender expression, or any other protected category under applicable federal, state, or local laws.
If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Talent.acquisition@onsemi.com for assistance.
Required
- Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)
- 10+ years of experience in digital IC design with strong RTL development background
- Expert-level proficiency in SystemVerilog RTL design
- Strong experience with Python for design automation and tool development
- Solid experience with UVM-based verification methodologies and testbench development
- Strong understanding of UPF, synthesis, STA, and timing signoff flows
- Experience working with DFT concepts and integration
- Strong cross-functional collaboration skills across design, verification, physical design, and product teams
Preferred
- Experience designing IO subsystems or peripheral architectures for microcontrollers or SoCs
- Experience with design generators, templated RTL, or hardware construction frameworks
- Exposure to AI/ML techniques applied to hardware design or verification workflows
- Experience building or deploying automated testbench generation and regression systems
- Familiarity with highly configurable or parameterized architectures
- Experience in automotive or safety-critical designs
Responsibilities
- Own the architecture and development of the IO subsystem, ensuring configurability and reuse across multiple products
- Define subsystem-level specifications, interfaces, and integration strategy aligned with platform and product requirements
- Define and implement parameterized and Python generator-based design approaches, enabling scalable and configurable subsystem instantiation
- Drive the creation of automatically generated testbenches and verification environments, leveraging UVM frameworks and AI-assisted techniques
- Develop high-quality SystemVerilog RTL, ensuring compatibility with automated generation flows and maintainability at scale
- Support synthesis, STA, and timing closure activities to ensure signoff-ready designs
- Collaborate with verification, DFT, and physical design teams to achieve first-time right silicon
- Apply AI/ML techniques to improve design productivity, including code generation assistance, verification acceleration, and design space exploration
- Drive PPA optimization while maintaining configurability and reuse targets
- Establish best practices for design automation, code generation, and methodology standardization across the organization