ENGR PRIN, DESIGN LAYOUT; DSGN
Design · Full-time
Bengaluru, Karnataka, India
Posted on Sep 9, 2026
We are looking for Principal Analog Layout Engineers to join our Image Sensor team.
The ideal candidate will have strong expertise in analog and mixed-signal layout design, with the ability to independently drive complex layout blocks, mentor junior engineers, and contribute to layout methodologies and quality improvements.
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
| We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work. |
- 12-15 years experience in analog layout design
- Strong hands-on experience with Cadence Virtuoso.
- Expertise in physical verification flows.
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Solid understanding of:
- Device matching and common-centroid techniques
- Symmetry and critical analog routing
- Shielding and noise isolation
- Power planning and substrate management
- ESD and reliability considerations
- Proven ability to independently handle complex analog layout blocks and drive closure.
- Strong debugging and problem-solving skills.
- Effective communication skills.
- Lead physical layout implementation of complex analog and mixed-signal blocks such as ADCs, PLLs, Bandgaps, References, LDOs, Bias circuits, and image sensor-related analog IPs.
- Independently own block-level layout activities from floorplanning through verification and final signoff.
- Drive layout architecture discussions, floorplanning strategies, matching requirements, power planning, shielding, and area optimization.
- Ensure high-quality execution through DRC, LVS, ERC, EM/IR, density, reliability, and other tapeout quality checks.
- Collaborate closely with circuit designers to optimize performance, area, and schedule.
- Identify layout-related risks early and propose mitigation plans.
- Mentor junior layout engineers and provide technical guidance on best practices and layout methodologies.
- Contribute to layout automation, productivity improvements, and development of reusable methodologies.
- Participate in design reviews and support project execution across multiple product generations.