Staff STA Engineer

SWIR Vision Systems
SWIR Vision Systems

Full-time

Bengaluru, Karnataka, India

Posted on Sep 27, 2026

Description
OnSemi is seeking a Staff STA Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications.

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onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.

More details about our company benefits can be found here:

https://www.onsemi.com/careers/career-benefits


We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.


Qualifications

BE in Electrical Engineering or related + 6 years of experience, or M.Tech + 5 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF
Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
Solid track record of releasing complex ICs to market
Ability to clearly articulate issues, challenges, and concerns to all levels of management
Must have good written and verbal cross-functional communication skills

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Responsibilities

STA Lead with expertise in timing constraints handling for different fullchip IO protocol (I2C, DDR, USB etc…)
Generating ECO for timing closure for complex multi power domain designs
Good experience in running STA regression with high number of modes/corners efficiently.
Power recovery with STA signoffDebug constraint issues in P&R environment
LEC/Low power checks experience
Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
Strong in problem solving with deep understanding of technical issues.
Candidate should have keen eye to improve existing flow and methods with positive impact on PPA.

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