DFT Principal Engineer
Full-time
Bengaluru, Karnataka, India
Posted on Sep 27, 2026
OnSemi is seeking a Principal Physical DFT Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications.
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onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
| We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work. |
Qualifications
- BS in Electrical Engineering or related + 12 years of experience, or MS + 11 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
- Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF
- Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
- Solid track record of releasing complex ICs to market
- Ability to clearly articulate issues, challenges, and concerns to all levels of management
- Must have good written and verbal cross-functional communication skills
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In this role, you will focus on the following:
- DFT Lead with expertise various Scan implementation like Stuck-At, MBIST, iJTAG, BSCAN, Transition, bridge faults
- Providing timing constraints for scan modes
- Pattern simulation with zero delay and SDF
- Coverage analysis and improvement suggestions to design
- Low power issues fix post DFT implementation
- Post silicon debug
- Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
- Strong in problem solving with deep understanding of technical issues.
- Candidate should have keen eye to improve existing flow and methods with positive impact on PPA.
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