External Manufacturing Staff Operation Engineer
Full-time
Suzhou, Jiangsu, China
Posted on Oct 20, 2026
onsemi is currently seeking an experienced Process Engineer to support and optimize wafer bumping & DPS manufacturing processes for high-volume semiconductor production. The successful candidate will be responsible for process development, process characterization, yield improvement, defect reduction, equipment qualification, and manufacturing support while ensuring compliance with quality and reliability requirements. Relevant bumping experience may include UBM, photolithography, plating, reflow, wafer thinning, WLCSP, Cu pillar, solder bump, micro-bump, or advanced packaging technologies.
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
| We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work. |
· Bachelor's Degree or higher in:
- Electrical Engineering
- Electronic Engineering
- Materials Science
- Chemical Engineering
- Mechanical Engineering
- Semiconductor Engineering
· Minimum 5 years of semiconductor manufacturing experience.
· Minimum 3 years of direct wafer bumping process experience.
· Strong knowledge of:
- Solder bump technology
- Cu pillar bumping
- WLCSP
- UBM process
- Electroplating
- Reflow process
· Experience in high-volume semiconductor manufacturing environment.
· Strong understanding of SPC, MSA, FMEA, Control Plan, 8D, and DOE methodologies.
· Hands-on experience in process troubleshooting and yield improvement.
· Proficient in statistical data analysis tools such as JMP, Minitab, or equivalent.
· Familiar with semiconductor quality standards and customer qualification requirements.
· Own and maintain wafer bumping processes to achieve yield, quality, cycle time, and cost targets.
· Develop, optimize, and sustain bump & DPS related processes including:
- UBM deposition
- Photolithography
- Electroplating
- Reflow
- Wet etch/strip
- Wafer thinning and grinding
- Wafer saw
- Final wafer inspection
· Conduct DOE, process characterization, and robustness studies for new products, materials, equipment, and process changes.
· Perform root cause analysis and implement corrective/preventive actions for yield, reliability, and defectivity issues.
· Lead failure analysis activities related to bump defects such as:
- Missing bump
- Non-wettable bump
- Bridging
- Voids
- Bump height variation
- Oxidation
- Delamination
- Cracking
· Establish SPC monitoring and process control plans.
· Support qualification activities, customer requirements, and manufacturing change management.
· Collaborate with Quality, Reliability, Product Engineering, Equipment Engineering, Suppliers, and Customers on technical issues.
· Evaluate and qualify new materials, bump masks, tooling, and equipment.
· Drive continuous improvement projects to enhance yield, productivity, and cost efficiency.
· Provide technical training and guidance to process technicians and manufacturing personnel.